ENTERING PROTECTED PIPELINE MODE WITHOUT ANNULLING PENDING INSTRUCTIONS
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Dec 19, 2024
filing date -
Dec 19, 2024
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status (Latency Note)
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Abstract
Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.
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