MULTIPLIER, MULTIPLY-ACCUMULATE CIRCUIT, OPERATIONAL CIRCUIT, PROCESSOR, AND CALCULATION APPARATUS
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Jun 19, 2024
filing date -
Jun 19, 2024
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Abstract
The present disclosure relates to a multiplier, a multiply-accumulate circuit, an operational circuit, a processor, and a calculation apparatus. The operational circuit includes an input processing circuit and the multiply-accumulate circuit. The input processing circuit receives a first number and outputs the first number as a first multiplicator for feeding into the multiply accumulate circuit by negating a sign bit of the first number in a case in which the first number is a signed number, and directly outputs the first number as the first multiplicator for feeding into the multiply-accumulate circuit in a case in which the first number is an unsigned number. The input processing circuit further receives a previously known second number and directly outputs the second number as a second multiplicator for feeding into the multiply-accumulate circuit. The multiply-accumulate circuit includes a multiplication subcircuit and an accumulation subcircuit.
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