3D CHIP PACKAGE STRUCTURE
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United States of America
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Issued Date -
Apr 3, 2025
app pub date -
Aug 1, 2024
filing date -
Aug 1, 2024
priority date (Note) -
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Abstract
A 3D chip packaging structure with a memory device. The memory device includes a memory wafer layer and a connecting layer. The memory wafer layer includes at least one memory partition. The connecting layer is disposed on one side of the memory wafer layer. The connecting layer includes at least one connecting quiet zone and at least one connecting area. The at least one connecting quiet zone and the at least one connecting area are corresponding to the at least one memory partition. The at least one connecting quiet zone is adjacent to the at least one connecting area. The area of the at least one connecting quiet zone is equal to or larger than the at least one connecting area.
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