PRE-ASSEMBLY WARPAGE COMPENSATION OF THIN DIE STRUCTURES

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250112173A1
SERIAL NO

18374577

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Abstract

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A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Eid, Feras Chandler, US 299 1201
Elsherbini, Adel Chandler, US 121 401
Jun, Kimin Portland, US 124 497
Li, Wenhao Chandler, US 85 699
Shi, Yi Chandler, US 143 760
Sounart, Thomas Chandler, US 26 23

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