INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250112120A1
SERIAL NO

18375084

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Abstract

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Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95052

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHAO, Robin Portland, US 24 6
CHU, Tao Portland, US 48 25
HUANG, Chiao-Ti Portland, US 29 4
HUNG, Ting-Hsiang Beaverton, US 19 4
JANG, Minwoo Portland, US 20 4
LIN, Chia-Ching Portland, US 227 960
LIN, Chung-Hsun Portland, US 181 2526
LUO, Yanbin Portland, US 17 13
MURTHY, Anand S Portland, US 351 6235
PACKAN, Paul Hillsboro, US 17 430
PULS, Conor P Portland, US 22 15
XU, Guowei Portland, US 69 186
ZHANG, Feng Hillsboro, US 1002 28040
ZHANG, Yang Rio Rancho, US 898 4769

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