LINE EDGE ROUGHNESS (LER) IMPROVEMENT OF RESIST PATTERNS

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250112056A1
SERIAL NO

18376053

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Exemplary semiconductor processing methods may include a substrate housed in the processing region. A layer of silicon-containing material may be disposed on the substrate, a patterned resist material may be disposed on the layer of silicon-containing material, and a layer of carbon-containing material may be disposed on the patterned resist material and the layer of silicon-containing material. The methods may include providing a hydrogen-containing precursor, a nitrogen-containing precursor, or both to a processing region of a semiconductor processing chamber, forming plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor, and contacting the substrate with the plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor. The contacting may remove a portion of the layer of carbon-containing material. The methods may include providing a fluorine-containing precursor to the processing region, forming plasma effluents of the fluorine-containing precursor, and contacting the substrate with the plasma effluents of the fluorine-containing precursor.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CA 95054

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ranjan, Alok San Ramon, US 154 2552
Sherpa, Sonam Dorje San Ramon, US 6 0

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation