SYSTEM AND MEMORY WITH CONFIGURABLE METADATA PORTION
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United States of America
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Issued Date -
Apr 3, 2025
app pub date -
Dec 12, 2024
filing date -
Dec 12, 2024
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status (Latency Note)
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Abstract
Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.
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