DATA LAYOUT CONSCIOUS PROCESSING IN MEMORY ARCHITECTURE FOR EXECUTING NEURAL NETWORK MODEL
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United States of America
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Apr 3, 2025
app pub date -
Dec 13, 2024
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Dec 13, 2024
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Abstract
The present disclosure relates to a processing in memory (PIM) enabled device for executing a neural network model. The PIM enabled device comprises a memory block assembly comprising a first array of memory blocks, a second array of memory blocks adjacent to the first array of memory blocks, a plurality of first data links associated with the first array of memory blocks and the second array of memory blocks, wherein each data link of the plurality of first data links communicatively couples two corresponding memory blocks of which are from the first array of memory blocks and the second array of memory blocks respectively, and a second data link communicatively coupled to the plurality of first data links. The data from a first memory block of the first array of memory blocks can be transferable to a second memory block of the second array of memory blocks via the plurality of first data links and the second data link.
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