Systems and Methods for Multi-Phase Clock Generation

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United States of America

APP PUB NO 20250110526A1
SERIAL NO

18979763

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Abstract

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Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDNO 8 LI-HSIN 6 ROAD HSINCHU SCIENCE PARK HSINCHU ROC 30077

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Wei Chih Hsinchu, TW 48 149

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