Importance

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Abstract

Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

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First Claim