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Abstract

Some embodiments of the present disclosure include a digital-to-analog conversion system configured to reduce inter-symbol interference (ISI) in high-speed continuous-time DACs. The system can include a main DAC with multiple sub-DACs, each configured to process a portion of a digital input sequence and generate part of an output waveform. To address ISI errors introduced by the sub-DACs, the system can include an ISI mitigation feedback loop. The ISI mitigation feedback loop can include an analog-to-digital converter (ADC) that generates a digital sequence from the output waveform and an analog correction signal generated by a correction DAC. A fractional decimation filter can be used to adjust a sampling rate and attenuate high-frequency components. A digital error estimator can generate an error cancellation sequence by correlating encoder information with the input sequence. The correction DAC can use the error cancellation sequence to generate the analog correction signal.

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First Claim