Quantized Bistable Resistively-coupled Ising Machine
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United States of America Patent
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Issued Date -
Mar 27, 2025
app pub date -
Jan 12, 2023
filing date -
Jan 12, 2023
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Abstract
A computation node comprises an input, an output, a bistable node, comprising an input and an output, the output configured to have at least two equilibrium output voltages, a first buffer circuit, having an input and an output, the buffer input connected to the bistable node and the buffer output connected to the computation node, the buffer circuit configured to provide a first output voltage when a voltage at the buffer input is below a threshold, and a second output voltage when the voltage at the buffer input is above the threshold, and a current conveyor node having an input connected to the computation node and an output connected to the bistable node, the current conveyor configured to hold its input at a constant voltage and mirror current received at the input into the input of the bistable node. A network of resistively-coupled computation nodes is also described.
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