SEMICONDUCTOR PACKAGE INCLUDING STRESS-REDUCTION CHAMFERS AND METHODS FOR FORMING THE SAME
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United States of America Patent
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Issued Date -
Mar 27, 2025
app pub date -
Sep 27, 2023
filing date -
Sep 27, 2023
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Abstract
A semiconductor package includes: a package substrate including a horizontal top surface; an interposer bonded to the top surface of the package substrate; a semiconductor die bonded to a top surface of the interposer, the semiconductor die including a bottom surface that faces the top surface of the interposer, and chamfers formed in corners of the bottom surface of the semiconductor die; and a molding layer surrounding the semiconductor die and filling the chamfers.
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