MEMORY AND OPERATING METHOD THEREOF

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United States of America Patent

APP PUB NO 20250104746A1
SERIAL NO

18829789

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Abstract

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Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified fixed-number-random-access mode, in which the memory array can be continuously read or written in response to receiving a fixed number of random access addresses; sequentially receiving the preset fixed number of access addresses via the data/address multiplexing line in succession; sequentially outputting data read in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates read operations, or sequentially receiving data to be written in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates write operations; and ending the mode by receiving an invalid chip enable signal.

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Patent Owner(s)

Patent OwnerAddress
GIGADEVICE SEMICONDUCTOR INCBEIJING

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
HU, Hong Beijing, CN 60 287
LI, Yang Beijing, CN 1182 7549
MA, Sibo Beijing, CN 4 7
ZHAO, Jianzhong Beijing, CN 6 6

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