SYSTEMS AND METHODS FOR ERROR DETECTION AND CONTROL FOR EMBEDDED MEMORY AND COMPUTE ELEMENTS
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United States of America Patent
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Mar 27, 2025
app pub date -
Oct 4, 2024
filing date -
Oct 4, 2024
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Abstract
Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.
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