Memory Sparing to Improve Chip Reliability
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United States of America Patent
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Issued Date -
Mar 27, 2025
app pub date -
Dec 5, 2024
filing date -
Dec 5, 2024
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Abstract
The mapping of system memory addresses to physical memory addresses is modeled as a two dimensional mapping array. Each element of the mapping array is assigned a system memory address and a physical memory address to which the system memory address is mapped. The mapping array is arranged to facilitate designation of a portion of the physical memory addresses as spareable physical memory addresses that are employed when there is a memory failure.
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