MASK OPTIMIZATION PREFERENTIALLY ACCOUNTING FOR OVERLAP REGIONS
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United States of America Patent
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Mar 27, 2025
app pub date -
Aug 23, 2024
filing date -
Aug 23, 2024
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Abstract
Some embodiments provide a method for optimizing a mask layout generated from a design layout of an IC. Based on an initial mask layout for a first layer, the method generates a simulated wafer image including shapes representing IC components of the layer, including a first component that has a relationship with a second component on a second layer of the design layout. The method identifies, in the simulated wafer image, (i) a first set of regions of a first shape of the first component that overlap with a second shape of the second component and (ii) a second set of regions of the first shape that do not overlap with the second shape. To improve overlap between the first shape's first set of regions and the second shape, the method modifies the initial mask layout to produce a modified mask layout.
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