SEMICONDUCTOR MEMORY DEVICE WITH A THREE-DIMENSIONAL STACKED MEMORY CELL STRUCTURE
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United States of America
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Mar 20, 2025
app pub date -
Nov 29, 2024
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Nov 29, 2024
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Abstract
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
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