FHE CHIP AND COMPUTING DEVICE
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United States of America
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Issued Date -
Mar 20, 2025
app pub date -
Sep 11, 2024
filing date -
Sep 11, 2024
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status (Latency Note)
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Abstract
Embodiments of this specification provide an FHE chip and a computing device. The FHE chip includes a MIN and n PEs, and n is an integer greater than 1. The n PEs are configured to execute n operation tasks that belong to a ciphertext operation in parallel in a process of performing the ciphertext operation on target ciphertext by the FHE chip, where the target ciphertext is obtained by processing raw data based on an FHE algorithm. The MIN is configured to support a first PE in transmitting switching data to a second PE, where the switching data belongs to an operation result generated by the first PE by executing the operation task, and the first PE and the second PE belong to the n PEs.
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