DELAY-LOCKED LOOP (DLL) WITH BINARY SEARCH LOCKING AND DEAD CLOCK DETECTION
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United States of America
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Issued Date -
Mar 20, 2025
app pub date -
Sep 20, 2023
filing date -
Sep 20, 2023
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Abstract
A system includes memory and at least one processor coupled to the memory and configured to receive a phase detector (PD) error signal. The PD error signal indicates a leading clock signal of at least two clock signals. The at least two clock signals are generated based on an input clock signal and a voltage control signal. The at least one processor receives a toggling signal indicating whether one of the at least two clock signals is toggling between clock cycles of the input clock signal. A code value is generated based on the PD error signal and the toggling signal. The at least one processor causes generation of the voltage control signal based on the code value.
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