BACKSIDE OFFSET GATE CONTACT FOR BACKSIDE SPACING
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United States of America
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Issued Date -
Mar 20, 2025
app pub date -
Sep 17, 2023
filing date -
Sep 17, 2023
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Abstract
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a front-end-of-line (FEOL) including a first source/drain (S/D) adjacent to a first gate. A device may include a backside interconnect below the FEOL, with a plurality of signal lines and a plurality of power lines. A device may include an offset gate contact electrically connected between the first gate and a first signal line of the plurality of signal lines, wherein the offset gate contact is located directly below the first S/D.
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