CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER
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United States of America
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Issued Date -
Mar 20, 2025
app pub date -
Sep 15, 2023
filing date -
Sep 15, 2023
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Abstract
An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit lines in different memory layers may share the same sense amplifier. The IC device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. A memory layer may be bonded with the CMOS layer through a bonding layer that provides a bonding interface between the memory layer and the CMOS layer.
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