HARDWARE ACCELERATOR, PROCESSOR, CHIP, AND ELECTRONIC DEVICE
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United States of America
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Issued Date -
Mar 20, 2025
app pub date -
Sep 11, 2024
filing date -
Sep 11, 2024
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Abstract
A hardware accelerator comprises a PE array, an internal buffer unit, and a data scheduler. The data scheduler obtains multiple image lines from the internal buffer unit and schedules the PE array to sequentially perform MAC (multiply-accumulate) operations on the multiple image lines. There are overlapping pixel lines between adjacent image lines, and the overlapping pixel lines are subjected to MAC operations in both of their adjacent image lines to which they belong. During the MAC operations on each image line, the PEs of the PE array are scheduled to perform MAC operations in tiles on multiple tiles included in each image line. For adjacent tiles, the operation result of the overlapping portion between the previous tile and the subsequent tile is cached, and combined with the operation result of the non-overlapping portion of the subsequent tile to form the MAC operation result of the subsequent tile.
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