NEUROMORPHIC COMPUTING CIRCUIT AND METHOD FOR CONTROL
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United States of America
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Issued Date -
Mar 20, 2025
app pub date -
Aug 15, 2024
filing date -
Aug 15, 2024
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Abstract
A neuromorphic computing circuit includes nodes including first and second nodes generating a spike including a counter for a spike existing time and a sender information, and a transmission array including transmission circuits, one or more of which is on the transmission path and forwards the spike. Each transmission circuit updates a counter value when forwarding the spike and sets, when detecting meeting of a first spike from the first to the second node and a second spike from the second to the first node, time difference based on the counter values, into the first spike. The second node includes a generation circuit specifying time difference equal or less than a first threshold among ones in the received spikes, accumulating connection strengths between the sender of third spikes set the specified differences therein and the second node, and generating a fourth spike when the accumulating result exceeds a second threshold.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
FUJITSU LIMITED | 1-1 KAMIKODANAKA 4-CHOME NAKAHARA-KU KAWASAKI-SHI KANAGAWA 211-8588 |
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
TAKANO, Shigeyuki | Ichikawa, JP | 5 | 28 |
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