Importance

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Abstract

One example provides a device comprising a FIFO data buffer comprising a load shift register, a request line encoder, a state machine, and one or more clocks to provide a clock signal. The load shift register comprises a plurality of register locations and is configured to shift data between at least two register locations controllable on at least one shift instruction and to load data into at least one of the register locations controllable on at least one load instruction. The request line encoder is configured to receive one or more requests each comprising a corresponding priority value, and to determine a request number value representing a number of requests to load into the load shift register. The state machine is configured to determine, based at least in part on the request number value, a state, one or more shift instructions, and one or more load instructions.

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First Claim