DUTY CORRECTION CIRCUIT, A CLOCK GENERATION CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DUTY CORRECTION CIRCUIT
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United States of America
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Issued Date -
Mar 20, 2025
app pub date -
Jan 26, 2024
filing date -
Jan 26, 2024
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Abstract
A duty correction circuit includes a first delay circuit, a second delay circuit, a dividing circuit, a duty detection circuit, and a delay control signal generation circuit. The first delay circuit is configured to delay a clock signal to generate a first delayed clock signal. The second delay circuit is configured to delay the clock signal based on a delay control signal to generate a second delayed clock signal. The dividing circuit is configured to divide the first and second delayed clock signals to generate a first to fourth phase clock signals. The duty detection circuit is configured to detect phases of the first to fourth phase clock signals to generate a duty detection signal. The delay control signal generation circuit generates the delay control signal based on the duty detection signal.
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