PIPELINE SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER RESIDUE AMPLIFIER OFFSET CANCELLATION
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United States of America
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Issued Date -
Mar 13, 2025
app pub date -
Jul 30, 2024
filing date -
Jul 30, 2024
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Abstract
A controller obtains a first calibrated gain of a residue amplifier. The residue amplifier amplifies a first residue voltage to a voltage corresponding to a first output code of a second stage of the pipelined ADC. The first residue voltage is output from a capacitive digital-to-analog converter (CDAC) of a first stage of the pipelined ADC. The controller obtains a second calibrated gain of the residue amplifier. The residue amplifier amplifies a second residue voltage to a voltage corresponding to a second output code of the second stage of the pipelined ADC. The second residue voltage is output from the CDAC of the first stage of the pipelined ADC. The controller determines a final calibrated gain of the residue amplifier based on the first calibrated gain and the second calibrated gain.
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