Importance

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Abstract

A lock detecting circuit includes a pre-clock detection signal generating circuit configured to detect phases of a first clock and a second clock to generate a first pre-clock detection signal and a second pre-clock detection signal based on the detected phases, a first clock detection signal generating circuit configured to generate a first clock detection signal by adjusting a pulse width of the first pre-clock detection signal, a second clock detection signal generating circuit configured to generate a second clock detection signal by adjusting a pulse width of the second pre-clock detection signal, and a lock control circuit configured to detect a phase difference between the first clock and the second clock, based on the first clock detection signal and the second clock detection signal to generate a lock signal.

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First Claim