Importance

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Abstract

An adjustable clock that may be implemented on a field-programmable gate array (FPGA). The adjustable clock may be highly accurate and stable, and may be adjustable in response to software commands. The adjustable clock may be configured to generate a clock signal that is synchronized in frequency and/or phase with a clock that is external to the FPGA, such as a Precision Time Protocol (PTP) clock. The FPGA may implement the adjustable clock with a number of elements as programmable logic, including a numerically-controlled frequency divider, a multi-tap delay line, logic configured to dynamically select, for each clock pulse, a delay of the multi-tap delay line, and a feedback loop to control the numerically-controlled frequency divider.

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First Claim