MEMORY DEVICE INCLUDING VOLTAGE GENERATING CIRCUIT AND OPERATION METHOD OF MEMORY DEVICE
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United States of America
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Issued Date -
Mar 13, 2025
app pub date -
Jan 19, 2024
filing date -
Jan 19, 2024
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Abstract
Disclosed is a memory device which includes a memory cell array that includes a plurality of memory cells, and a peripheral circuit configured to perform a plurality of operations on the memory cell array by using a plurality of operating voltages. The peripheral circuit includes a voltage generating circuit including a first pump block, a second pump block, and a common pump block. The voltage generating circuit connects the first pump block and the common pump block in parallel to generate a first operating voltage among the plurality of operating voltages and connects the common pump block and the second pump block in series to generate a second operating voltage among the plurality of operating voltages. The common pump block is configurable to match the first pump block, the second pump block, or both, as needed.
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