INTERCONNECTIONS FOR 3D MEMORY

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250087249A1
SERIAL NO

18811059

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Abstract

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Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC2805 EAST COLUMBIA ROAD BOISE ID 83706

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tanzawa, Toru Tokyo, JP 309 5305

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