METHOD AND TENSOR TRAVERSAL ENGINE FOR STRIDED MEMORY ACCESS DURING EXECUTION OF NEURAL NETWORKS
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United States of America
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Mar 13, 2025
app pub date -
Nov 22, 2024
filing date -
Nov 22, 2024
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Abstract
A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.
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