APPARATUS AND METHODS FOR BACK-TO-BACK STATE MACHINE CONTROLLER BUS OPERATIONS
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United States of America
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Issued Date -
Mar 13, 2025
app pub date -
Sep 13, 2023
filing date -
Sep 13, 2023
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Abstract
An apparatus is provided that includes a memory structure including non-volatile memory cells, a first processor and a second processor. The first processor is configured to provide a plurality of sets of commands to a second processor to perform memory operations on the non-volatile memory cells. The second processor is configured to execute the sets of commands and provide a control signal to the first processor. The first processor is further configured to provide the sets of commands to the second processor based on a status of the control signal. The second processor is further configured to control the status of the control signal so that the second processor executes sets of commands with no idle time between consecutive sets of commands.
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