CLOCK GENERATING CIRCUIT AND CLOCK DISTRIBUTION NETWORK AND SEMICONDUCTOR APPARATUS INCLUDING THE CLOCK GENERATING CIRCUIT
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United States of America
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Issued Date -
Mar 13, 2025
app pub date -
Nov 22, 2024
filing date -
Nov 22, 2024
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Abstract
A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.
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