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United States of America
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Issued Date -
Mar 13, 2025
app pub date -
Aug 23, 2024
filing date -
Aug 23, 2024
priority date (Note) -
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status (Latency Note)
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Abstract
Provided is a circuit for managing a first clock signal clocking a timer adapted to being controlled by a processor clocked by a second clock signal. When the processor is off, the first clock signal is equal to a third clock signal having a frequency lower than the frequency of the second clock signal. When the processor is on, the first clock signal is equal to a fourth signal having a rising edge at each rising edge of the second clock signal directly following a rising edge of the third clock signal.
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