METHODS OF IMPROVING PMOS TRANSISTOR PERFORMANCE

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250081593A1
SERIAL NO

18459582

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Abstract

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Methods of manufacturing electronic devices, such as transistors (negative metal-oxide-semiconductor (NMOS) transistors (e.g., an N-metal stack) and positive metal-oxide-semiconductor (PMOS) transistors (e.g., a P-metal stack)) are described. Embodiments of the disclosure are directed to methods of improving PMOS transistor performance by inhibiting N-metal layer growth. The present disclosure provides two types of processes to reduce or inhibit N-metal layer growth. The disclosure provides methods which include forming a self-assembled monolayer (SAM) on the metal surface (e.g., titanium nitride (TiN)) of the PMOS, and methods which include forming a silicon-containing layer such as silicon oxide (SiOx) on the TiN surface. These two types of processes significantly reduce or inhibit the subsequent growth of an N-metal layer, such as titanium aluminum carbide (TiAlC), on the TiN surface of the PMOS.

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Patent Owner(s)

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APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhuyan, Bhaskar Jyoti San Jose, US 98 526
Chen, Shih Chung Cupertino, US 48 518
Devrajan, Janardhan Santa Clara, US 8 1
Gandikota, Srinivas Santa Clara, US 214 6856
Garg, Sourav Santa Clara, US 4 19
Li, Lu Santa Clara, US 118 612
Lin, Yongjing San Jose, US 28 81
Liu, Zhihui Sunnyvale, US 35 95
Sha, Haoyan San Jose, US 6 1
Yan, Haoming Santa Clara, US 8 7

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