GATE DIELECTRIC FEATURES IN HIGH-VOLTAGE IC DEVICES AND METHODS OF FORMING THE SAME
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Mar 6, 2025
app pub date -
Aug 29, 2023
filing date -
Aug 29, 2023
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
Some embodiments relate to an integrated circuit device incorporating an etched recessed gate dielectric region. The integrated circuit device includes a substrate including a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed over the gate dielectric region. The gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. The second upper surface includes a perimeter portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully