CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER WITH REDUCED INTER-CELL INTERFERENCE
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Mar 6, 2025
app pub date -
Sep 3, 2024
filing date -
Sep 3, 2024
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A DAC cell circuit includes: at least a DAC cell, including: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node. The dead-band switch is controlled by a signal which is periodic with respect to a frequency equal to an input data rate of the DAC cell, and the dead-band switch is open during a data transition.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully