PARASITIC CAPACITANCE MITIGATION CIRCUIT FOR RELAXATION OSCILLATORS
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United States of America
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Mar 6, 2025
app pub date -
Aug 29, 2024
filing date -
Aug 29, 2024
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Abstract
A parasitic capacitance mitigation circuit for a relaxation oscillator. The parasitic capacitance mitigation circuit includes a first switch coupled across a parasitic capacitance of a resistive sensing element and a second switch coupled between the parasitic capacitance and a reference voltage node. The parasitic capacitance mitigation circuit includes a pulse generator configured to: monitor a voltage across the parasitic capacitance; detect a voltage transient across the parasitic capacitance; and generate a pulse control signal in response to detecting the voltage transient. In response to the pulse control signal, the first switch opens and the second switch closes to discharge the parasitic capacitance through the second switch.
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