MEMORY
Number of patents in Portfolio can not be more than 2000
United States of America
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Issued Date -
Mar 6, 2025
app pub date -
Nov 16, 2024
filing date -
Nov 16, 2024
priority date (Note) -
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status (Latency Note)
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Abstract
A memory includes: a first-stage amplifier circuit, connected to a bit line and a complementary bit line, and configured to amplify a voltage difference between the bit line and the complementary bit line; a second-stage amplifier circuit, connected to a local data line and a complementary local data line, further connected to a global data line and a complementary global data line, amplifying a voltage difference between the local data line and the complementary local data line after the local data line is connected to the bit line and the complementary local data line is connected to the complementary bit line, and generating a voltage difference between the global data line and the complementary global data line; and a driving circuit, connected to the local data line and the complementary local data line, and amplifying the voltage difference between the local data line and the complementary local data line.
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