Low Latency Offloading of Collectives over a Switch
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United States of America
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Issued Date -
Mar 6, 2025
app pub date -
Aug 31, 2023
filing date -
Aug 31, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
A device includes a plurality of processing elements (PEs). A symmetric memory is allocated in each of the plurality of PEs. The device includes a switch connected to the plurality of PEs. The switch is to: receive, from a first processing element (PE) of the plurality of PEs, a message that includes a buffer offset, compute, based on the buffer offset, a first memory address of a first buffer in a first symmetric memory of the first PE and a second memory address of a second buffer in a second symmetric memory of a second PE of the plurality of PEs, and initiate, based on the first memory address and the second memory address, a direct memory access operation to access the first buffer and the second buffer.
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