Contact Structures for Dual-Thickness Active Area SOI FETS
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United States of America
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Issued Date -
Feb 20, 2025
app pub date -
Aug 17, 2023
filing date -
Aug 17, 2023
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Abstract
Structures and methods for better optimizing the performance of all the circuitry of an SOI IC. Embodiments include SOI IC having dual-thickness active areas, such that digital and non-RF analog circuitry may be fabricated on a relatively thin active layer while RF circuitry may be fabricated on a relatively thick active layer. Fabrication of RF circuitry on the relatively thick active layer allows for improvements to the RON*COFF figure of merit for the FET devices, and for optimizations not feasible for RF circuitry fabricated on a relatively thin active layer. Structures and methods for two-level shallow-trench isolation (STI) structures and electrical contacts are disclosed. Some embodiments may include a substrate contact extending from the substantially planar upper surface of a dielectric layer overlaying the thin and thick active areas to at least the BOX layer.
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