PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH SOLDER INTERCONNECTS
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United States of America
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Issued Date -
Feb 20, 2025
app pub date -
Aug 18, 2023
filing date -
Aug 18, 2023
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Abstract
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.
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