STRUCTURE FOR DELAMINATION MITIGATION IN A SEMICONDUCTOR DEVICE

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250062246A1
SERIAL NO

18450943

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Abstract

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Disclosed are devices in which a die, such as a system-on-chip (SoC) die is attached to an interposer with a mold. Unlike convention devices, the contact area for adhesion is increased by providing vertical surfaces in addition to lateral surfaces for attachment. In so doing, possibility of delamination is decreased significantly.

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Patent Owner(s)

Patent OwnerAddress
QUALCOMM INCORPORATED5775 MOREHOUSE DRIVE SAN DIEGO CA 92121-1714

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
BUOT, Joan Rey Villarba Escondido, US 55 24
LEE, Sang-Jae San Diego, US 37 362
WANG, Zhijie San Diego, US 130 483
WE, Hong Bok San Diego, US 143 828

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