GAN RELIABILITY BUILT-IN SELF TEST (BIST) APPARATUS AND METHOD FOR QUALIFYING DYNAMIC ON-STATE RESISTANCE DEGRADATION

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250060404A1
SERIAL NO

18936841

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • Assignment data not available. Check PTO

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHEN, Kun-Lung Chu Pei City, TW 38 404
CHERN, Chan-Hong Palo Alto, US 230 1822
HUANG, Ruo-Rung Hsin-Chu, TW 3 1
LAI, Yu-Ann Hsin-Chu, TW 3 1
YANG, Chun-Yi Hsinchu City, TW 28 82

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation