MEMORY DEVICE
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United States of America
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Issued Date -
Feb 13, 2025
app pub date -
Jul 23, 2024
filing date -
Jul 23, 2024
priority date (Note) -
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Abstract
A memory device includes a plurality of first peripheral circuits, a stack memory cell array and a first address circuit. The first peripheral circuits are disposed on a first chip, wherein the first chip has a plurality of first pads. The stack memory cell array is disposed on a second chip, wherein the second chip has a plurality of second pads. The second pads are coupled to the stack memory cell array, and respectively coupled to corresponding first pads. The first address circuit is disposed on the second chip, coupled to the stack memory cell array, and disposed under the stack memory cell array.
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