BACK-END-OF-LINE MEMORY DEVICES AND METHODS FOR OPERATING THE SAME
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United States of America
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Issued Date -
Feb 13, 2025
app pub date -
Aug 10, 2023
filing date -
Aug 10, 2023
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Abstract
A memory device includes a plurality of memory cells. Each of the plurality of memory cells includes a capacitor configured to store an amount of electrical charges, and a plurality of transistors electrically coupled to the capacitor. Based on a pulse signal, a first subset of the plurality of transistors are configured to form a first conduction path, and a second subset of the plurality of transistors are configured to form a second conduction path. The amount of electrical charges is configured to be altered through the first conduction path and the second conduction path.
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