INTEGRATED CIRCUIT AND METHOD OF OPERATING SAME
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United States of America
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Issued Date -
Feb 13, 2025
app pub date -
Nov 20, 2023
filing date -
Nov 20, 2023
priority date (Note) -
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Abstract
An integrated circuit includes a first set of memory cells configured to store a first set of data, a second set of memory cells configured to store a second set of data, a first set of input output (IO) circuits coupled to the first set of memory cells, a second set of IO circuits coupled to the second set of memory cells, a first error correction code (ECC) circuit configured to store a first number of ECC bits, a second ECC circuit configured to store a second number of ECC bits; and a first ECC encoder/decoder circuit configured to correct at least a first number of errors in the first set of data and the second set of data based on the first number of ECC bits and the second number of ECC bits.
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