DEVICE AND METHOD TO GENERATE BIAS VOLTAGES IN NON-VOLATILE MEMORY
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United States of America
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Feb 13, 2025
app pub date -
Aug 16, 2024
filing date -
Aug 16, 2024
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Abstract
The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.
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