CLOCK DISTRIBUTION NETWORK, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE CLOCK DISTRIBUTION NETWORK
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United States of America
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Issued Date -
Feb 13, 2025
app pub date -
Jan 8, 2024
filing date -
Jan 8, 2024
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Abstract
A clock distribution network includes an input control circuit and a clock tree. The input control circuit is configured to generate a control input clock signal based on an input clock signal and a low power mode signal. The clock tree is configured to generate an output clock signal by buffering the control input clock signal. When the low power mode signal is enabled, the input control circuit is configured to change a DC level of the control input clock signal.
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